A Silicon on Insulator (SOI) substrate is used as a substrate for integrated circuit (IC) manufacturing. Compared with a bulk silicon substrate, the SOI substrate may provide the ICs with low parasitic capacitance, high integration density, low short channel effect and fast speed, and dielectric isolation between components in the ICs. Use of SOI substrates may eliminate the parasitic latch-up effect, which often occurs when a bulk silicon substrate is used.
Currently, SOI substrates may be formed by a SIMOX (i.e., Separation by Implanted Oxygen) process, a silicon wafer bonding process, and a smart cut process. FIGS. 1-4 are cross-sectional structure diagrams illustrating a conventional process for forming an SOI substrate using a smart cut process.
Referring to FIG. 1, a first monocrystalline silicon sheet 10 and a second monocrystalline silicon sheet 20 are provided. A silicon oxide layer 30 is formed on the first monocrystalline silicon sheet 10. Referring to FIG. 2, hydrogen ions 40 are implanted into the first monocrystalline silicon sheet 10 via a silicon oxide layer 30. Referring to FIG. 3, the silicon oxide layer 30 and the second monocrystalline silicon sheet 20 are cleaned and bonded together. Referring to FIG. 4, the bonded structure including the first monocrystalline silicon sheet 10 and the second monocrystalline silicon sheet 20 is then annealed by a high-temperature annealing process. Due to existence of the implanted hydrogen ions, the first monocrystalline silicon sheet 10 is split into a third monocrystalline silicon sheet 11 and a fourth monocrystalline silicon sheet 12. As shown in FIG. 4, the third monocrystalline silicon sheet 11, the silicon oxide layer 30, and the second monocrystalline silicon sheet 20 form the SOI substrate. The third monocrystalline silicon sheet 11 serves as a top silicon layer of the SOI substrate, while the second monocrystalline silicon sheet 20 serves as a substrate silicon layer of the SOI substrate.
Micro-bubbles are often used to split the first monocrystalline silicon sheet 10 into the third monocrystalline silicon sheet 11 and the fourth monocrystalline silicon sheet 12. Large surface roughness may then be obtained for the split surface of the third monocrystalline silicon sheet 11 and the surface of the fourth monocrystalline silicon sheet 12. When a semiconductor device is formed directly on the split surface of the third monocrystalline silicon sheet 11 (which serves as the top silicon layer of the SOI substrate), defects are easy to occur due to the high surface roughness of the third monocrystalline silicon sheet 11. This may cause the semiconductor device to be scrapped. Therefore, after the formation of the SOI wafer, it needs to perform chemical mechanical polishing on the surface of the monocrystalline silicon sheet 11 to obtain small roughness of the surface of the monocrystalline silicon sheet 11.
However, to improve electrical properties of the SOI substrate, an Extremely Thin SOI (ETSOI) substrate has become used in IC manufacturing. The top silicon layer on the insulating layer of the ETSOI substrate is thin. MOS transistors formed on this ETSOI substrate may have low short-channel effect. Device isolation is achieved by LOCOS (i.e., local oxidation of silicon) or shallow STI (i.e., shallow trench isolation). However, it is difficult to control the thin thickness of the top silicon layer by conventional methods such as the smart cut process. In addition, when grinding or polishing the surface of the top silicon layer using the chemical mechanical polishing process to reduce the surface roughness of the top silicon layer, the thin top silicon layer may be overly ground or polished and defects may occur when subsequently forming semiconductor devices on the ETSOI substrate. The resulting semiconductor devices may thus be scrapped.